High-Throughput, Low-Memory Applications on the Pica Architecture

This paper introduces Pica, a fine-grain, message passing architecture designed to efficiently support high-throughput parallel applications. This focus on high-throughput applications allows a small local memory of 4096 36-bit words. The architecture minimizes overhead for basic parallel operations. An operand-addressed context cache and round-robin task manager allow single cycle task swaps. Fixed-sized activation contexts simplify storage management. Word-tag synchronization bits provide low-cost synchronization. Several applications have been developed for this architecture including thermal relaxation, matrix multiplication, JPEG image compression, and positron emission tomography image reconstruction. These applications have been implemented and executed on the Pica architecture using an instrumented instruction-level simulator. Using these results, the architectural features of Pica are evaluated.